1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems utilising register renaming so as, for example, to facilitate out-of-order processing.
2. Description of the Prior Art
It is known to provide data processing systems in which register renaming mechanisms are used whereby register specifiers for an architectural destination register (i.e. the destination register as specified within an instruction of the instruction set) is mapped to a physical register provided within the system for use in executing the associated program instruction. Such techniques are useful in avoiding write-after-read (WAR) hazards, write-after-write (WAW) hazards and in facilitating the reordering of instructions at execution time. The technique is also useful in enabling a data processing system to speculate over unresolved exception points within the program instruction flow. It will be appreciated that register renaming is useful for a variety of reasons, and is not limited in its application to out-of-order processing.
In known register renaming techniques a processor core renames an architectural register specified by an instruction thereby allocating a new physical register to be used in place of an architectural register for each architectural destination register specifier encountered within each instruction. Once this allocation/mapping is done, then the processor core can execute the instruction using the physical registers in the “physical register world”.
There are a number of drawbacks associated with known register renaming techniques. The number of physical registers which may be provided is finite and the register renaming mechanism can run short of available physical registers to be used for mapping to architectural registers. This is particularly the case in data processing systems in which program instructions can involve the use of a large number of registers, e.g. the LDM (load multiple) instructions of the ARM instruction set of the processors produced by ARM Limited of Cambridge, England. If the register renaming mechanism runs out of available physical registers to use for the remapping then this can stall the instruction pipeline. This problem gets worse as pipeline depth increases as there will be more program instructions concurrently “in-flight” and consuming physical registers.
One way of reducing this problem would be to provide a larger number of physical registers. However, the provision of such physical registers consumes circuit area and power, which is in itself disadvantageous.
Another problem associated with register renaming techniques is that the register renaming processing mechanisms themselves consume power and have a finite bandwidth. Signal values transitioning within the register renaming mechanisms to perform mappings for every architectural destination register encountered within an instruction represent a significant source of energy consumption. Furthermore, when some instructions may have a large number of architectural destination registers, either a disadvantageously large register renaming mechanism has to be provided in order that these renaming operations can all be performed in parallel, or the renaming operations have to be serially performed with a consequent potential for stalls and/or delayed processing.